1. Field of the Invention
The invention relates to a phase lock loop (PLL) circuit. Particularly, the invention relates to a PLL circuit capable of quickly and accurately locking a required frequency and phase.
2. Description of Related Art
Phase lock loop (PLL) circuit has a long history of development process and still plays a key role in technique discussions due to its wide application and high development potential. In brief, a basic function of the PLL circuit is to use an oscillation source with an extremely low variation to serve as a basic reference, and drive a device with a variable frequency under a feedback function of a closed loop control system, so that the frequency of the device is quickly and stably maintained at a same phase with the oscillation source, i.e. the frequency is phase locked.
Moreover, most of the current PLL circuits apply a dual-loop design with a coarse tune loop and a fine tune loop. Under consideration of stability, a large resistor and a large capacitor may be used to construct the coarse tune loop in a typical analog dual-loop PLL, so as to generate a pole at a very low frequency. Moreover, in order to acquire a locking stability, the fine tune loop is often considered in design of a dual-loop PLL. On the other hand, a voltage control oscillator (VCO) having a low frequency gain (Kvco) is usually used in the conventional dual-loop PLL for advantages such as a low phase noise and an excellent power supply rejection ratio (PSRR). However, a problem of a slow locking response speed exists in the conventional dual-loop PLL due to a fixed and excessively limited bandwidth of a coarse tune low-pass filter of the coarse tune loop.